The BeMicro CV comes with 1 giga_bit_ of RAM, not 1 giga_byte_. This was originally specified incorrectly on Arrow's website but appears to be fixed now. The major gotcha here is that you need to use Altera's hard IP memory controller--which only functions untethered for 1 hour unless you pay an exorbitant amount of money for the full version of Quartus II or you purchase the individual IP for a similarly exorbitant amount of money. Both are priced to exclude hobbyists, so if you expected to make use of the onboard DDR3 RAM, be prepared to tether or pay.
The squares in the photo are 1". The board is tiny!
The BeMicro CV also came with a different version of the Cyclone V FPGA than spec'ed: 5CEFA2F23I7N instead of 5CEFA2F23C8N. The supplied one is an industrial one, with a wider temperature range (-40 °C to 100 °C) and a slightly faster speed grade (7 as opposed to 8). For more info on the Cyclone V, see the device overview, datasheet, and handbook.
LED Pin Assignment
The pin assignments given in the datasheet are wrong. The correct assignments are:
- USERLED_0: N1
- USERLED_1: N2
- USERLED_2: U1
- USERLED_3: U2
- USERLED_4: W2
- USERLED_5: AA1
- USERLED_6: AA2
- USERLED_7: Y3
80-pin Card Edge Connector
The 80-pin card edge connector (shared with the BeMicro SDK) is proprietary
and the manufacturer (Samtec) doesn't appear to sell the correct version. A document on the Linear Technologies website suggests the Samtec MEC-140-02-L-D-RA1 for the BeMicro SDK, but it appears to have a plastic divider in the center, where no corresponding cutout is present in the card edge.
UPDATE: The above mentioned connector is NOT the correct one. miguelvp on the EEVblog forums kindly informed me that the correct card edge connector is the Samtec MEC6-140-02-L-D-RA1, which can be had for $10. Various other connectors seem to be available. Additionally, miguelvp explained that the BeScope bundle not only includes the BeMicro CV, but the BeScope daughterboard, SDP Interposer, and an oscilloscope probe--for the same $50! What a steal!
Programming the Board
An old version of the datasheet includes schematics for the board. I've verified that the open hardware design for the Propeller 1 P8X32A runs successfully. There's also a video of another guy (not me) playing music with it and syso has a post on building and tweaking the P8X32A.
To program the board, I'm using Altera's Quartus II Web Edition on Debian.
The full package for Quartus II Web Edition comes with the ModelSim Altera Starter Edition.
The simulator's output is what you'd expect from the code (and a mirror-image of the behavior on the board).
Logic onboard is active low. Tactile switches and DIP switches are normally open and the input pins on the FPGA are pulled high. In order to have the LEDs correspond to the usual interface conventions (un-inverted logic): display inputs (on an LED) unmodified; and in logic, swap ANDs for ORs, ORs for ANDs, and XNOR for XOR.
UPDATE: miguelvp over at the EEVblog forums wrote an excellent tutorial on using a top level schematic to avoid swapping gates in the Verilog code. It's based on the code listed below, but using the logic functions as you would expect. You should follow his tutorial instead of using the code below. Thanks miguelvp!
tact_b are mapped to pins H18 and J18 respectively.
`timescale 1ns / 1ps module hello_world( input wire tact_a, input wire tact_b, output wire [7:0] led ); // Turn off unused LEDs assign led[4:2] = 3'b111; // Status LEDs for tactile switches assign led = tact_a; assign led = tact_b; // Beware: inverted logic onboard. Will work backwards in the simulator. assign led = tact_a | tact_b; // AND assign led = tact_a & tact_b; // OR assign led = !(tact_a ^ tact_b); // XOR endmodule